Quantum

Modular Neural Decoder for Surface Code Memory and Logic on Superconducting Processors

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Based on a feed excerpt; full article content has not been acquired. Source evidence retrieved 06/10/2026, 04:13:25 UTC.

Briefings

A new modular graph-recurrent decoder was introduced for surface code memory and logic on superconducting processors. It outperforms minimum-weight perfect matching (MWPM) on IBM Nighthawk processors at distances 3 and 5, and closely matches AlphaQubit's data. The framework was tested on two settings: continuous tuning of measurement error rates via variable pre-readout rotation, and decoding $ZZ$-merge lattice-surgery experiments between distance-3 surface-code patches. The model was trained on single-GPU academic resources, demonstrating portability across hardware and observables.

Key points

• The modular graph-recurrent decoder was trained on single-GPU academic resources and successfully ported to IBM Nighthawk processors.
• The decoder outperformed MWPM at distances 3 and 5 on IBM Nighthawk processors and closely matched AlphaQubit's data.

Context and limitations

The study covers only surface code memory and logic on superconducting processors, with limited coverage of other hardware types and logical operations.

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