Quantum
FNO-Based Inverse Co-Design of Semiconducting Quantum-Dot Devices
Publication: quant-ph updates on arXiv.org
Author: Marek Rychetsky, Valentin Duruisseaux, Freya Shah, David L. Craig, Ming Ni, Georgios Katsaros, Taylor L. Patti, Anima Anandkumar, Natalia Ares
Source published: 06/11/2026, 05:00:00 UTC
Briefing created: 06/11/2026, 05:57:22 UTC
Based on a feed excerpt; full article content has not been acquired. Source evidence retrieved 06/11/2026, 05:13:24 UTC.
Briefings
A new differentiable inverse co-design framework using a Fourier neural operator (FNO) enables the rapid optimization of gate voltages and electrode layouts for semiconductor quantum dots. The FNO surrogate predicts charge-density fields with a relative L2 error of 0.6% and achieves 17,000-fold speed-ups over CPU-based simulators on GPUs, allowing for the generation of vertically and horizontally elongated double-dot geometries from initial conditions. This approach addresses the lack of exhaustive design space exploration in existing fabrication processes, offering a route to engineer qubit-relevant operating properties before physical fabrication.
Key points
- The FNO surrogate predicts charge-density fields with a relative L2 error of 0.6%.
- The framework enables 17,000-fold speed-ups over CPU-based simulators on GPUs.
Context
Gate-defined semiconductor quantum dots are promising building blocks for scalable spin-based quantum processors. Existing architectures rely on repeated fabrication and testing, which does not exhaustively explore the design space. This study presents a differentiable inverse co-design framework to jointly optimize gate voltages and electrode layouts, addressing the need for targeted qubit properties prior to fabrication.
Limitations
The study relies on a semiclassical Thomas-Fermi electrostatic simulator for reference data. Performance gains from batched inference are noted but specific batch sizes are not detailed. The framework is validated on GPU hardware; performance on other architectures is unknown. The 0.6% L2 error is a relative test metric and does not guarantee absolute accuracy across all device types. No fabrication constraints were applied during the simulation phase.
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